02 Feb, 2016 Presentation
The Real-Time Bidding (RTB) protocol serves hundreds of billions of ads daily on about 100 demand-side platforms (DSPs), moving hundreds of Terabytes (TB) of data back and forth through ad exchanges to serve ad impressions to audiences browsing content from publishers on websites and mobile applications. The RTB protocol uses text-based tags in Hypertext Transfer Protocol (HTTP) to distribute bid requests and collect responses via millions of individual unicast Transport Control Protocol (TCP) sessions between the exchanges and DSPs.
In the past, Wall Street also used text-based protocols to disseminate market data and send orders via the text-based Financial Information eXchange (FIX) protocol. More recently, the financial markets have moved to using binary protocols to disseminate market data messages over UDP/IP multicast. Protocols like the Nasdaq TotalView ITCH, for example, send messages in binary to more efficiently transport data. Stock exchanges also use multicast to reach multiple endpoints without duplicating data across individual sessions. Together, these improvements provide transparency and enable better price discovery.
Today’s Advertising Technology (Ad Tech) requires time to parse a bid request, look up relevant data about a user, evaluate an opportunity, decide on the value, then bid a price to serve an impression. The response time is bounded by the acceptable delay in loading an impression on a user’s browser. Due to the overhead of RTB, advertisers only get one chance to bid their Cost Per Impression (CPI).
Stock exchanges, however, are not limited to a single round of bidding. Prices are discovered by allowing all participants to continuously submit bids, ask for offers, and react to changes in the market. Multiple rounds of bidding are known to generate better prices than a single round. Financial markets are so efficient that many rounds of bidding could be performed within the time bound of a typical Ad Tech auction.
By monitoring live market data feeds and computing an order book with Field Programmable Gate Array (FPGA) logic, auctions can be performed with sub-microsecond latency. Tracking the open orders by all participants ensures that the market is fair, liquidity is made available, transactions are profitable, and the system is capable of sustaining high volumes of traffic.
To optimally participate in such markets, Algo-Logic has developed multiple Gateware Defined Networking (GDN) algorithms and components to support ultra-low-latency processing functions in heterogeneous computing systems. For example, an order book that runs in FPGA logic in an IBM POWER8 server has been built which includes an ultra-low-latency 10 Gigabit/second Ethernet MAC, a market data feed handler, a fast Key-Value Store (KVS) for tracking orders, and logic to sort the prices of the bid and ask offers. To efficiently transfer the results from the FPGA logic to coherent shared memory in an IBM POWER8 server, we use the Coherent Accelerator Processor Interface (CAPI). By implementing the entire feed processing module and order book in logic, the system enables software to directly receive market data snapshots with microsecond latency.
As a member of the Open Power Foundation (OPF), Algo-Logic provides an open Application Programming Interface (API) that allows software developers to easily select which markets they wish to track and how often they want updates to be transferred to shared memory. Together, this FPGA-accelerated heterogeneous platform with compact binary protocols and multicast feed distribution provides a fast, transparent, and efficient platform that dramatically improves real time auctions.
John W. Lockwood, CEO of Algo-Logic Systems, Inc., is an expert in building FPGA-accelerated applications. He has founded three companies focused on low latency networking, Internet security, and electronic commerce and has worked at the National Center for Supercomputing Applications (NCSA), AT&T Bell Laboratories, IBM, and Science Applications International Corp (SAIC). As a professor at Stanford University, he managed the NetFPGA program from 2007 to 2009 and grew the Beta program from 10 to 1,021 cards deployed worldwide. As a tenured professor, he created and led the Reconfigurable Network Group within the Applied Research Laboratory at Washington University in St. Louis. He has published over 100 papers and patents on topics related to networking with FPGAs and served as served as principal investigator on dozens of federal and corporate grants. He holds BS, MS, PhD degrees in Electrical and Computer Engineering from the University of Illinois at Urbana/Champaign and is a member of IEEE, ACM, and Tau Beta Pi.
Artem Iakovlev is a member of technical staff at Algo-Logic systems. He holds a BS from UCLA and a MS from Columbia University and is a member of IEEE and Eta Kappa Nu.