|Start||End||Room to be confirmed||50 Seats|
|13:00||14:00||Streaming Framework Meeting|
|15:30||17:00||Design Thinking Workshop||Personalized Medicine Working Session (Zaid Al-Ars)|
|Start||End||200 seats (plenum)||50 seats||40 seats|
|08:30||09:00||Arrival & registration|
|09:00||09:45||Integrated Solutions Workgroup (Randall Ross, Canonical)||System SW Workgroup (Chris Austen)|
|11:00||11:45||Technical Steering Committee Meeting (Jeff Brown, IBM)||unused||unused|
|12:30||13:00||Restricted lunch for Tech Steering Committee
Registration for main audience
|Time||Presentation File (click to view)||Title||Speaker||Role|
|13:00||Opening Introduction||John Zannos and Calista Redmond||OpenPOWER Foundation Chair and President|
|13:15||OpenPOWER Roadmap||Steve Fields and Rani Borkar||IBM (IBM Fellow and Chief Engineer Power Systems & Vice President of OpenPOWER Development)|
|13:30||The IBM - Barcelona Supercomputing Deep Learning Center||Mateo Valero||Director, Barcelona Supercomputing Centre|
|13:45||Smarter Innovation at Scale at the Hartree Centre||Neil Morgan||Programme Manager|
|ATOS Group/Bull historic partnership with IBM||Gilles Delample||Director, Global Escala, Atos/Bull|
|Bluebee: High Performance Genomics-as-a-Service Using Elastic Acceleration||Zaid Al-Ars||Co-founder, Bluebee|
|14:30||GPU-Accelerated Database: Convergence of Business Analytics & AI||Charles Sutton||Managing Director, Europe, Kinetica|
|15:00||OpenStack out in the open||Ildiko Vancsa||Ecosystem Technical Lead, OpenStack Foundation|
|14:45||Swift Object Store Deployment on OpenPOWER||Jacob Caspi (AT&T), Tom Mathews (IBM), Christian Reis (Canonical)|
|15:15||Deploying and Operating OpenStack Clouds on OpenPower||Edward Shvartsman||IBM (Senior Technical Staff Member, Power Systems)|
|16:00||New OpenPOWER Resources for European Developers and Students||Prof. Dr. Helmut Krcmar|
|16:15||The POWER of Open - Open Platforms Shape the Future||Georg Greve||Kolab (CEO & Founder of Free Software Foundation Europe)|
|16:30||Introducing the OpenPOWER Ambassador Program||Randall Ross||Community Manager, Ubuntu/Canonical|
|16:45||CAPI SNAP Framework / Developer Challenge Winners||Bruce Wile & John Zannos|
|17:00||Fast Forward Evolution||Fabrizio Magugliani||E4 Computer Engineering|
|17:15||The Accelerated Data Centre||Dr. Tim Lanfear||NVidia|
|17:30||Accelerating Deep Learning training with POWER8, P100, and NVLink||Scott Soutter||Offering Manager, High Performance Computing and Deep Learning|
|17:45||Next Generation Performance and Scalability with Mellanox "Smart" Interconnect and OpenPOWER||Chloe Ma||VP CloudX Program|
|18:00||OpenPOWER Technical Steering Committee Update||Jeff Brown||Technical Steering Committee Chair|
|18:15 - 21:30||Welcome Reception|
OpenBMC, A Reference Firmware Stack | Chris Austen (IBM) | Click for presentation
OpenPOWER is open with the exception of the BMC. That all changes with the introduction of OpenBMC. This talk will focus on what it is and how the community organized team of developers are using it on many OpenPOWER servers along with the future directions including P9, OpenStack and OpenCompute. Audience: OpenStack Ansible and Ironic developers, Server Design architects, System Management architects, Manufactures, Cloud providers. People will leave the talk wanting to get engaged with the OpenPOWER Foundation workgroups knowing they have a voice.
Measuring and Managing Power Consumption | Todd Rosedahl (IBM) | Click for presentation
This presentation will include an overview of the power, thermal, and performance data that can be collected from OpenPOWER servers via various methods, including a newly open sourced profiling tool called AMESTER. The power/performance knobs, such as processor frequency, that are under the control of the On Chip Controller (OCC) will be described and the overall OCC power management functions will be highlighted.
Ensuring POWER9 Success with System-level Simulation for Early Software Verification | Saif Abrar (IBM)
Success of POWER9 systems depends on timely availability of various software stacks. Absence of suitable hardware poses a verification challenge for new firmware and drivers. This presentation describes a behavioral system-level simulation environment, made of a POWER simulator and behavioral models of devices and interconnects; these are used for early verification of the software. Various product-level software like Linux, OPAL, IBM Power Hypervisor drivers, IBM Flexible Service Processor firmware, SBE stack, Hostboot driver and P7/P8 stacks have been debugged and verified successfully before actual HW, shortening the HW bringup cycle to save cost and time. It is versatile to also validate the post silicon tests for HW IPs in the system.
OpenPOWER Performance | Alex Mericas (IBM) | Click for presentation
OpenPOWER builds on the strengths of the Power Architecture through open collaboration. We will discuss how IBM enables partners to exploit the performance of OpenPOWER offerings. This session will introduce the performance characteristics of the 1-Socket and 2-Socket reference designs and give an overview of performance results for these systems. To support OpenPOWER Partners IBM provides Performance Enablement, which will be discussed.
IBM XL C/C and Fortran Compilers for OpenPOWER | Shereen Ghobrial (IBM) | Click for presentation
IBM XL C/C and Fortran compilers are built on an industry wide reputation for robustness, versatility, standards compliance and performance. This presentation will provide the latest update on IBM XL compilers for OpenPOWER, which will cover major features to enhance portability, compatibility and performance. XL C/C for OpenPOWER is built with Clang front end components and IBM highly optimizing backends. It provides improved GCC compatibility and language standards support for easier migration and enhanced capability. This presentation will introduce IBM XL C/C and Fortran support for GPU exploitation through CUDA and OpenMP accelerator extension, and address how applications can benefit from the IBM XL compilers’ optimization.
Emerging Workload Performance Evaluation on Future Generation OpenPOWER Processors | Saritha Vinod (IBM) | Click for presentation
Open source innovation has resulted in rapid emergence of many significant real-world workloads. Next generation processor design need to evaluate the emerging workload behavior to ensure optimal performance. Hence emerging workload traces capturing the essence of these applications are essential to gather insights on key characteristics and allow performance evaluation in future generation of processors. There are unique challenges in generation of traces and using them for evaluation. How do we ensure that the collected trace is truly a representation of the workload behavior? What kind of performance evaluations can be done using these traces? In this talk we present about various techniques and challenges in generating representative workload traces and how they enable performance evaluation for future generation of processors.
OpenPOWER: A Community Tour | Randall Ross (Canonical) | Click for presentation
An overview of the OpenPOWER community for ISV’s (and developers). If you’re thinking about OpenPOWER and need resources and inspiration, this talk will highlight what’s available, what’s happening, and why OpenPOWER is the “next big thing”.
The CAPI SNAP Framework for Programmers | Bruce Wile (IBM) | Click for presentation
Since the release of the CAPI Technology and associated Developer Kit in 2014, the realm of FPGA acceleration has been dominated by those with the computer engineering skills of VHDL and Verilog. We are announcing an open source, OpenPOWER project that provides an acceleration platform for programmers, called “CAPI SNAP Framework” (Storage, Networking, and Analytics Programming). The framework makes it easy for developers to create specialized accelerated algorithms in C++, Go and other high level programming languages– utilizing the leading-edge CAPI technology. This session will briefly describe the framework, the “acceleration action” programming paradigm, and the simple APIs used to invoke accelerated actions.
How to become a SuperVessel / Developer Cloud? | Yong Hua Lin and Peter Hofstee (IBM) | Click for presentation
This brief presentation will cover Supervessel, an OpenStack-based OpenPOWER cloud accelerated with GPUs and FPGAs. Infrastructure available for academia and developers in China, and the US, and also a recent addition in Europe will be highlighted. A number of examples of Supervessel-based projects that leverage GPU and FPGA acceleration will be covered. Finally we explain how to get started if you not only want to use Supervessel, but plan to build one of your own!
A 101 Guide to Heterogeneous, Accelerated, Data Centric Computing Architectures | Allan Cantle (Nallatech) | Click for presentation
Data Centric terms have recently become popularized in the world of computing, but this shift in lexicon has not really been well communicated. This presentation aims to provide a 101 guide to the disadvantages of traditional Von Neumann, CPU Centric Architectures and their 25 year history of “patching up” and “working around” the well understood Von Neumann Memory Wall Syndrome with increasingly complex caching hierarchies and structures. The presentation will close with highlighting how IBM OpenPOWER members are all feverishly collaborating to make this seismic shift in the computing industry happen as smoothly and quickly as possible to bring far more computational horse power for far less energy & cost become a true reality.
ConTutto – A flexible memory interface in the OpenPOWER ecosystem | Thomas Roewer (IBM) | Click for presentation
ConTutto is a configurable platform for innovation in the memory subsystem of an IBM Power System node. By replacing the memory buffer ASIC of a commercial IBM Power server with a high-end FPGA connected to the processor’s memory link, we enable multiple system-level innovations including 1) Systems Research with new memory technologies, such as MRAM and NVDIMMs, and 2) Near-memory acceleration of data flowing between processor and memory. In this talk, we will present details of the ConTutto platform, and show system-level implementations of both use-cases. This work is partially funded through the Department of Energy FastForward-2 contract.
Everyone agrees: computers will stop getting faster or cheaper. What do we do now? | Rob Taylor (Reconfigure) | Click for presentation
In a world increasingly driven by data and analysis, the future depends on the cost and efficiency of computing. Technology entrepreneur Rob Taylor shows the limits of current designs and a possible path forward using hardware acceleration.
The CAPI SNAP Framework Deep Dive | Bruce Wile (IBM) | Click for presentation
Since the CAPI Developer Kit debuted in November, 2014, we’ve seen multiple infrastructure and ecosystem enablement contributions. These, in turn, have fostered the growth in the number of CAPI accelerators. This presentation will take a quick look back at the ecosystem growth before focusing on the next generation CAPI SNAP*) Framework being introduced at the OpenPOWER Summit Europe. The framework makes it easy for developers to create specialized accelerated algorithms in C++, Go and other high level programming languages.
*) Storage, Networking, and Analytics Programming
Leveraging OpenPOWER and FPGAs to accelerate machine vision and learning | Lisa Liu (Xilinx) | Click for presentation
Leveraging coherent memory integration via IBM’s CAPI interface, IBM POWER8 CPUs combined with Xilinx FPGA accelerators provide higher compute efficiency, lower power utilization and total cost of ownership for critical workloads in data centers and HPC. In this session, we will provide an overview of how FPGA acceleration can enhance POWER systems for a broad range of applications with a particular emphasis on machine vision and learning workloads such as image recognition and video scaling. We include a theoretical study, leveraging UC Berkeley ParLab Roofline models, as well as present some recent results from a selection of prototypes on a POWER8 system.
New Memory Controller and Very Low Latency Network for Accessing Low Latency (200-400ns) NVM Storage | Luiz M Franca-Neto (HGST) | Click for presentation
Current Datacenters use Ethernet/IP fabric and switches to access NAND-Flash based local and remote storage. 75us readout latency NAND-Flash are accessed through additional 5us or 10us Ethernet switch latencies in the datacenter fabric. However, with emerging low latency NVM-based storage with readout latencies ~1,000x times shorter, at ~200ns, Ethernet/IP fabric and switches are clearly inadequate. We present and discuss a new very low latency fabric (~100ns) topology of critical local and remote access (RMA) for these emerging NVM storage solutions. We outline the necessary and viable changes in the design of OpenPOWER memory controller to enable an RMA service launched from WRITE/READ commands on the memory bus.
Phase Change Memory Access in OpenPOWER Systems using CAPI | Nikolaos Papandreou (IBM) | Click for presentation
Novel forms of storage class memory (SCM), such as phase change memory (PCM), promise low latency and small granularity of R/W access while offering high endurance and storage density. In this work we demonstrate low latency PCM access in OpenPOWER systems via CAPI. Our platform consists of OpenPOWER servers (IBM S824L, Tyan Palmetto) equipped with CAPI-enabled FPGA cards and custom non-volatile DIMMs made of PCM chips. In the talk, we will give an introduction to PCM as the top contender for SCM and present the architecture of our prototype system and FPGA-based CAPI-enabled PCM controller. Moreover, we will present latency and performance measurements using our custom PCM DIMMs as well as custom HW that emulates future PCM technology.
OpenPOWER Ready | Jeff Brown (IBM) | Click for presentation
OpenPOWER Ready™ is a mark used by the OpenPOWER Foundation to enable ecosystem product developers to indicate their product has been shown/demonstrated to meet a minimum set of characteristics and should be interoperable with other OpenPOWER Ready products. Come and hear more about this program and how your organisation can be involved.
Increasing the Density of Apache Spark in the Cloud Through Coherently Attached Flash on POWER8 | Thomas Hubregtsen (IBM) | Click for presentation
Traditionally, disk bandwidth has been the limiting factor in Big Data processing systems. In Spark, this problem is alleviated by using in-memory computation, thereby providing the user with a high amount of bandwidth. Unfortunately, memory has become the most expensive part of a computer system which typically limits the available capacity. Spark starts spilling to disk once the available memory is exhausted which can have a significant impact on the performance. In IBM Research we aim to leverage user-addressable Flash storage as a cheaper alternative to increasing the memory while providing better performance compared to hard disk drives. We implemented an initial version of Spark that uses Flash attached through the CAPI in POWER8.
Highly Scalable OpenPOWER Big Data Framework for DNA Analysis Pipelines | Zaid Al-Ars (Bluebee) | Click for presentation
OpenPOWER vendors and users as well as Operations/DevOps tool providers in our community can benefit and further engage to provide feedback and collaborate in this effort.
Deep Learning on Power | Samuel Cozannet (Canonical) | Click for presentation
Artificial intelligence will be a core component of a large majority of future applications. We present a reference architecture to start training neuronets in minutes on Power, as well as an example workflow on an example Network Intrusion Detection application, from gathering the training data, to performing training and finally moving the pre trained model to production.
Low Latency Edge Supercomputers for Connected Vehicles and Video Analytics Using OpenPower and RapidIO | Devashish Paul (IDT) | Click for presentation
The main reason for Mobile Edge Computing is it place computing resources close to end users to reduce the round trip latency between transaction initiation and application success without congesting 4G and 5G networks. Latency is not only limited to physical distance, but also the logical “distance” between computing elements inside the Edge Computer, which can be the difference between application success and failure, or as minimum, unsatisfactory delivery of the MEC enabled use case. As both Operators and Hyperscale Cloud Data Center owners try to work together to deliver more optimized network configurations to enable these use cases, in this presentation we will discuss low latency solutions at the edge. The presentation covers HPC like low latency heterogeneous computing appliances that can be placed at the wireless network access point, in the C-RAN or in the Central office, enabling a variety of applications that will be dependent on low latency computing using IBM Power CPUs, accelerators and RapidIO interconnect. The presentation covers the Connected Vehicle offload project that IDT is conducting at 5G Lab Europe where the MEC solution is built to manage vehicles and fleet data in a cell coverage area. The presentation also covers the real time object recognition and video analytics use case as well as broadcast video with Edge Computing.
POWER9 chip technology | Jeff Stuecheli (IBM) | Click for presentation
This presentation describes features of the POWER9 family, with optimizations for one- and two-socket servers, DDR4 direct-attached memory, PCI Express Gen 4, and multisocket enterprise servers with robust buffered memory systems. The design includes a new core microarchitecture featuring execution-slice technology, delivering enhanced performance with improved execution efficiency. The new design includes intelligent features for optimizing cloud workloads and improves virtualization efficiency. It features a robust set of accelerated heterogeneous computing technologies, enabling innovative solutions in the OpenPOWER ecosystem.
The Academia Discussion Group (ADG) within the OpenPOWER Foundation is an academic forum, which mainly targets academic members of the foundation but is open for all other members. The goals of ADG are to provide training and exchange of experience and know-how, to provide a platform for networking among academic members, to work on the engagement of the HPC community and to enable co-design activities. In this session we will give an overview on some of the ADG activities, provide information on the IBM academia program, present selected high-lights from using OpenPOWER technologies and architectures for science and close with an outlook on future opportunities from a supercomputing centre’s perspective.
The OpenPOWER Foundation is pleased to be working with the OpenStack Summit. As we market these events together we recommend that you purchase a Full Pass or the Keynote and Markeplace Pass to be able to attend the OpenStack Summit. At this time there will be no charge for the OpenPOWER Summit.
The OpenStack Summit has also been gracious enough to let us access their room reservation system for hotels. Rooms are filling up fast so please reserve today. https://www.openstack.org/summit/barcelona-2016/travel/#hotels
The OpenStack Summit is the most important gathering of IT leaders, telco operators, cloud administrators, app developers and OpenStack contributors building the future of cloud computing. Hear business cases and operational experience directly from users, learn about new products in the ecosystem and participate in hands-on workshops to build your skills. Attended by thousands of people from more than 50 countries, it’s the ideal venue to plan your cloud strategy and share knowledge about architecting and operating OpenStack clouds.www.openstack.org/summit/barcelona-2016/