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The IBM® POWER9™ processor is a superscalar symmetric multiprocessor designed for use in servers and large-cluster systems. It uses 14 nm technology with 17 metal layers. The POWER9 processor supports direct-attach memory. It supports a maximum symmetric multiprocessing (SMP) size of two sockets and is...

The POWER Service Layer to Accelerator Functional Unit (PSL / AFU) interface communicates to the acceleration logic running on the FPGA. Through this interface, the PSL offers services to the AFU. The services offered are cache-line oriented and allow the AFU to make buffering versus...

DESCRIPTION The Coherent Accelerator Processor Interface (CAPI) on IBM POWER8 systems is a new means for solution architects to gain system-level performance. CAPI connects a custom acceleration engine to the coherent fabric of the POWER8 chip. The hybrid solution has a simple programming paradigm while delivering...