Power Vector Intrinsic Programming Reference version 1.0.0_prd3
** Commenting period closes August 9, 2020 **
The Power Vector Intrinsic Programming Reference version 1.0.0_prd3 represents the review draft for a new specification, derived from and also expanding upon the vector documentation contained in the the 64-Bit ELF V2 ABI Specification: Power Architecture specification.
The purpose of this document is to provide a guide for vector programming on OpenPOWER systems, with an emphasis on examples of best practices. It further provides a reference for intrinsics provided by compliant compilers on OpenPOWER systems.
This document is a Standard Track, Work Group Specification work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
Linux on Power Architecture Reference – A PAPR Linux Subset – Review Draft
This is the review draft of the Linux on Power Architecture Reference version 2.9_pre7
The purpose of this document is to detail a stable platform architecture to be used by platforms defined by the POWER ISA Specification.
This document is a Standard Track, Work Group Specification work product owned by the System Software Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document. It was created using the Master Template Guide version 1.0.0. Comments, questions, etc. can be submitted to the public mailing list for this document at [email protected].
Please note the full indexed HTML version of the LoPAR document will be uploaded shortly – we are resolving a minor website issue. For now please refer to the PDF
OpenPOWER IO Design Architecture (IODA) Version 3 WG Specification version 3.0_prd1
** Commenting period closes June 19, 2020 **
The purpose of the I/O Design Architecture, version 3 (IODA3) specification is to describe the chip architecture for key aspects of PCI Express® (PCIe)-based host bridge (PHB) designs for IBM® POWER9™ systems.
This document is a Standard Track, Work Group Specification work product owned by the Hardware Architecture Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
I/O Design Architecture (IODA3) Compliance: Test Harness and Test Suite (TH/TS) version 1.0-PRD
** Commenting period closes June 19, 2020 **
The purpose of the OpenPOWER I/O Design Architecture, version 3 (IODA3) Compliance Test Harness and Test Suite (TH/TS) specification is to provide the test suite requirements to be able to demonstrate OpenPOWER I/O Design Architecture, version 3 (IODA3) compliance for POWER9 (TM) systems. It describes the tests required in the test suite and a test harness needed to execute the test suite. It also describes the successful execution of the test suite, including what it means for an optional feature to fail.
This document is a proposed Standard Track, Work Group Specification work product owned by the Compliance Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.
Coherent Accelerator Interface Architecture Version 2 (CAIA2) specification version 2.0_prd1
** Commenting period closes June 19, 2020 **
The Coherent Accelerator Interface Architecture Version 2 (CAIA2) specification defines the Coherent Accelerator Interface Architecture (CAIA) for the IBM® POWER9 systems. The information contained in this document enables various CAIA-compliant accelerator implementations to meet the needs of a wide variety of systems and applications. Compatibility with the CAIA enables applications and system software to migrate from one implementation to another with minor changes.
This document is a Standard Track, Work Group Specification work product owned by the Hardware Architecture Workgroup and handled in compliance with the requirements outlined in the OpenPOWER Foundation Work Group (WG) Process document.